Papers

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Signal Processing at 250 MHz Using High-Performance FPGA's

ABSTRACT

This paper describes an application in high-performance signal processing using reconfigurable computing engines: a 250 MHz cross-correlator for radio astronomy. Experimental results indicate that CMOS FPGA's can perform useful computation at 250 MHz. The notion of an "event horizon" for FPGA's leads to clear design constraints for high-speed application developers, and can be applied to a variety of real-time signal processing algorithms. Recent estimates indicate that higher-performance FPGA's available early in 1998 can attain speeds of over 300 MHz using 20% fewer logic elements than current designs.

The results of this design work provide important clues on how to improve FPGA architectures for signal processing at hundreds of MHz. Direct routing channels between logic elements can significantly increase performance. Routing architectures with four-way symmetry allow for rotations and reflections of sub-circuits needed for optimal packing density. Experimental results indicate that clock buffering often limits the top speed of the FPGA. Wave pipelining of clock distribution network may improve FPGA performance.

Keywords: FPGA, real-time signal processing, correlators, programmable logic, manual partitioning and placement, event horizon. https://sites.google.com/a/rapidprototypesinc.com/www/papers/stereovis-pdf/corr256.pdf?attredirects=0&d=1

 

Real-Time Stereo Vision on the PARTS Reconfigurable Computer
ABSTRACT

This paper describes a powerful, scalable, reconfigurable computer called the PARTS engine. The PARTS engine consists of 16 Xilinx 4025 FPGAs, and 16 one-megabyte SRAMs. The FPGAs are connected in a partial torus-each associated with two adjacent SRAMs. The SRAMs are tightly coupled to the FPGAs so that all the SRAMs can be accessed concurrently. The PARTS engine fits on a standard PCI card in a personal computer or workstation.

Figure 1: The PARTS engine. The first application implemented on the PARTS engine is a depth from stereo vision algorithm that computes 24 stereo disparities on 320 by 240 pixel images at 42 frames per second. Running at this speed, the engine is performing approximately 2.3 billion RISC-equivalent operations per second, accessing memory at a rate of 500 million bytes per second and attaining throughput of over 70 million point ´ disparity measurements per second. https://sites.google.com/a/rapidprototypesinc.com/www/papers/stereovis-pdf/stereoVis.pdf?attredirects=0&d=1